Vendor-Invariant Integer Inference for MindChain: Handshake v0 — Dual-Implementation Bit-Exactness of a Frozen Integer Profile on Real Weights, and the Open Cross-Vendor Gate

Date: 2026-07-10 Research corpus codename: NOOSPHERE. Provenance: Compiled from noosphere/research/nel-b1-determinism-memo.md (field survey, B1 verdict) and the Handshake v0 lab nel-real-inference/ (README + runs/silu_clip.json, runs/second_impl.json, runs/divergence_probe.json, runs/integer_generation_16.json, runs/schedule_gate.json, runs/llama_compare.json, runs/integer_24layer_prompt.json) — every number below was re-verified against its source JSON on 2026-07-10; unless a label says otherwise, all values carry that date.

Abstract

MindChain's neural lane (NEL) requires that a disputed inference resolve to one bit-pattern regardless of who computed it, on what silicon, with what loop nest. The field survey (B1 memo) establishes the diagnosis: every documented source of GPU inference nondeterminism — cuBLAS heuristic algorithm selection, split-K partial-sum combining, split-KV attention scheduling, batch-size-dependent tensor-core instruction selection — is floating-point reduction-order variance PAPER; in a genuinely integer profile, addition and max are associative and commutative, so bit-exactness is free by construction THEORY. Handshake v0 tests this on real weights: the frozen profile QWEN-Q8-DYADIC-Q16-v0 (profile_id 1ce6c47fd57f3d338104a09f95b1610a75c6fd865b353a7c843426059e7b81d9) runs the released Qwen2.5-0.5B-Instruct Q8_0 checkpoint with exact int64 arithmetic and committed LUTs. Two independently derived GEMM implementations — row-order versus column-stream — reproduce all 24 layer digests and the final logits bit-exactly MEASURED, and five adversarial schedules of a layer-0 GEMM yield one digest while an FP32 shadow of the same computation splinters into 4 distinct bit patterns MEASURED. A 16-token greedy divergence from llama.cpp CPU at step 6 is root-caused to a quantized-logit tie inside measured FP cross-implementation noise — llama.cpp's own CPU and Vulkan backends split on the same token pair, and the integer profile matches Vulkan 16/16 MEASURED. A SiLU LUT error/clip baseline is created (3,502,080 gate activations) and shows the committed NEL-L0 harness table is too narrow for this model class MEASURED. What Handshake v0 does not show is the program's Gate 1: no GPU integer kernel ran, no NVIDIA hardware was touched, and cross-vendor bit-identity remains the open falsifier (E-NEL-01).

Claims

Label discipline (ch08 §5.4): MEASURED = values read back from the run artifacts in this repository; PAPER = reported by an external primary source cited in the B1 memo; THEORY = proven or argued, exercised at lab scale but not adversarially at target scale. Denominators travel with numerators. All values dated 2026-07-10 unless stated.

• C1 MEASURED. A frozen integer inference profile executes a real released checkpoint end to end. QWEN-Q8-DYADIC-Q16-v0 (profile_id 1ce6c47fd57f3d338104a09f95b1610a75c6fd865b353a7c843426059e7b81d9) runs Qwen2.5-0.5B-Instruct from the released Q8_0 GGUF (sha256 ca59ca7f13d0e15a8cfa77bd17e65d24f6844b554a7b6c12e07a5f89ff76844e): every FP16 block scale frozen into Q24, Q16 int64 activations, exact int64 accumulation, Decimal-committed LUTs for RoPE/softmax/SiLU; all nonlinear and rounding choices are hashed into the profile_id. Source: nel-real-inference/README.md, lineage anchored in runs/integer_24layer_prompt.json.
• C2 MEASURED. Independent-implementation determinism holds on real weights. Two structurally different matmul/accumulation derivations of the profile — row-order (FrozenQwen.gemm: row chunks outer, per-block einsum partials, explicit per-block scalar accumulation) and column-stream (ColumnStreamQwen.gemm, derived independently: column blocks outer, one vectorized (T,32)@(32,rows) exact int64 matmul per block) — produce equal layer digests 24/24, equal final logits arrays, equal final hidden sha256 (177d822e4cd84e1d…, both implementations), and both match the preserved runs/integer_24layer_prompt.json digests (lineage 1ce6c47f…): digests_equal=TRUE, preserved_run_digests_match=TRUE, gate PASS (exit 0). Wall time 10.64 s (row-order) vs 13.87 s (column-stream). Source: runs/second_impl.json.
• C3 MEASURED. Adversarial schedule invariance holds where the FP negative control fails. On the layer-0 GEMM of a 4-token prefix, five schedules — canonical, reversed, tiled_shuffled, split_k, tree_walk — produce the identical digest ce837db86d26cfbf… with 0/5 schedules showing any mismatched cell (integer_schedule_gate=TRUE). The FP32 shadow of the same computation under the same five schedules produces 4 distinct bit patterns (f02f0e3b, f62f0e3b, 01300e3b, fb2f0e3b; fp32_shadow_diverged=TRUE). Source: runs/schedule_gate.json.
• C4 MEASURED, baseline-creating. SiLU LUT clipping baseline, 3,502,080 FFN gate activations (24 layers × 30 prompt tokens × 4864 intermediate), real-unit activation range [−31.87, +44.27], scored against stdlib float SiLU. Frozen-profile LUT (65537-entry, Q11 input clipped to ±16, Q16 output — the LUT the profile executes): max abs err 28.268280, mean abs err 6.798e-05, 41/3,502,080 clip events; all large errors are positive-side clips (x > 16 ⇒ err ≈ x − 16); layer 21 owns the worst case (act max 44.2683 → err 28.2683; 30 of the 41 clips), layer 3 next (act max 31.0021 → err 15.0021; 4 clips). The committed NEL-L0 harness LUT (layer_ref.silu_lut(), ±8 domain, Q4 output): max abs err 36.330780, mean abs err 1.828e-02, 1,166/3,502,080 clips — 28× the clip rate, and the Q4 output grid alone costs ~1.8e-02 mean error. Honest reading: the committed harness table is too narrow and too coarse for this model class; the frozen profile's ±16/Q16 table is the better baseline, and even it needs a wider positive domain. No prior threshold existed; this run creates the baseline. Source: runs/silu_clip.json.
• C5 MEASURED. The single greedy-decode divergence from llama.cpp CPU is a quantized-logit tie within FP rounding distance, not profile drift. runs/integer_generation_16.json: integer profile and llama.cpp CPU agree on generated tokens 0–5 (matching_prefix=6/16 compared) and split at step 6 — integer picks 374 (" is"), llama.cpp CPU picks 25963 (" reflects") on identical context. Root-cause probe (runs/divergence_probe.json, llama logprobs captured live, llama_greedy_honest=TRUE): llama.cpp CPU gap (25963 − 374) +0.213574; llama.cpp Vulkan fa0 gap on the same pair −0.075470 — llama's own two backends split on exactly this pair; integer-profile gap −0.016586 (Q16: 1322070 − 1323157 = −1087). Pair drift CPU frame → integer frame 0.230160 < measured FP cross-implementation noise 0.237414 (max common-top20 logprob delta, CPU vs Vulkan fa0, steps 0–6). The CPU decision margin at step 6 (0.2136) is the minimum of all seven steps (4.717, 3.246, 1.304, 3.089, 4.393, 0.317, 0.214) — the sequence broke at its weakest decision, as a tie should. The integer profile's 16-token generation is identical to llama.cpp Vulkan fa0 16/16 (integer_matches_vulkan_16_of_16=TRUE). Classification: quantized-logit tie within FP rounding distance; residual bounded to ≤ 0.23 logits on this pair, a band inside which llama.cpp's FP backends themselves have no ground truth.
• C6 PAPER → THEORY. The B1 verdict: every documented mechanism of GPU inference nondeterminism — cuBLAS/cuBLASLt heuristic selection, split-K/stream-K accumulation, load-adaptive split-KV attention, batch-size-dependent MMA instruction selection — is FP reduction-order variance PAPER: Thinking Machines He et al. 2025; cuBLAS docs; vLLM/SGLang integrations. Same-platform FP determinism costs 1.2–2.1× in production stacks PAPER: SGLang 34.35% avg; TML 26 s → 42–55 s, and the only measured cross-hardware bit-exact FP artifact (Verde/RepOps) is FP32-only, NVIDIA-only-evaluated, at +58% to +218% overhead on Llama-1B PAPER. In an integer profile, addition and max are associative and commutative, so any split plan, tile order, or batch size produces identical bits — bit-exactness is free by construction THEORY; C2 and C3 are that theory exercised on real weights at CPU lab scale. No artifact anywhere composes the known primitives into a cross-vendor bit-exact transformer profile, and nobody has published an NVIDIA/AMD/CPU bit-for-bit result for any transformer PAPER, B1 memo §7. Source: noosphere/research/nel-b1-determinism-memo.md.

Gate 1 — the open cross-vendor gate. The program's clock is gates, not dates. Handshake v0 shows CPU dual-implementation bit-exactness plus adversarial schedule invariance on real weights. It does NOT show a full integer forward pass on any GPU, NOT NVIDIA hardware (nothing here touches CUDA), and NOT cross-vendor execution. Bit-identical integer inference across CPU/AMD/NVIDIA silicon is Gate 1 of the program and it is OPEN — everything in this paper is evidence toward it, not a substitute for it. The exact next falsifier is E-NEL-01. (The llama.cpp Vulkan runs used in C5 are FP GPU execution used as a second reference frame, not integer-on-GPU.)

First silicon datapoint (E-NEL-01b, added later the same build, 2026-07-10). The AMD leg is no longer zero-evidence: on a consumer AMD Radeon RX 6600 XT (RDNA2, Vulkan via wgpu-native), i32 GEMM is bit-exact against an arbitrary-precision CPU reference at four shapes up to 1.07 G MACs, with identical digests under forward-k, reverse-k, and split-K decompositions — exactly the reduction-order freedoms that break FP — and two's-complement wrap exact through 55,854 overflowing accumulators (falsifier row 7 exercised; no deviation found) MEASURED 2026-07-10, gate1-gpu-lab/. Scope honesty: GEMM kernels, not the full frozen profile; one vendor; no DP4A/tensor-core int8 fast paths. Gate 1 stays open — this is the matrix's first datapoint, not its closure.

Non-claims. No full-profile GPU run (E-NEL-01b covers GEMM kernels only); no NVIDIA hardware; no cross-vendor run (Gate 1, above). No accuracy claim beyond the 16-token greedy probe — G3 accuracy re-validation at target shape remains open per the B1 gap table. No performance claim: the lab forward pass is Python + numpy at ~10.6–13.9 s per 30-token prefill on CPU, a referee-speed reference, not a serving stack. No serving integration, no batching, no KV-cache paging. Tokenizer/sampler byte-spec (B1 G7) is pinned only to the extent the fixed prompt exercises it.

Construction

The frozen profile. QWEN-Q8-DYADIC-Q16-v0 freezes every numeric choice of a 24-layer Qwen2.5-0.5B-Instruct forward pass into a hashable spec: the released Q8_0 GGUF's FP16 block scales are frozen into Q24 fixed-point at load; activations are Q16 in int64; GEMM accumulation is exact int64 (no saturation inside the dot product); RoPE, softmax, and SiLU evaluate through Decimal-committed lookup tables; every rounding and tie rule is part of the profile document, and the whole is hashed into profile_id = 1ce6c47f…. Determinism claims attach to the profile_id, not to any implementation: an implementation conforms iff its layer digests match.

Probe 2 — second implementation (second_impl_gate.py). The falsifiable statement behind "the spec, not the loop, defines the answer" is that a second, independently derived implementation reproduces the bits. Only gemm was re-derived — row-chunks-outer with per-block einsum partials and explicit scalar accumulation versus column-blocks-outer with one vectorized exact int64 matmul per block; everything else is shared byte-identically, so a digest mismatch could only come from order-of-accumulation semantics leaking into results. Both implementations run in one process on the fixed 30-token prompt across all 24 layers; per-layer digests, final logits, and final hidden hashes are compared, then checked against the preserved first-run lineage.

flowchart TD
    G["released Q8_0 GGUF weights, sha256 ca59ca7f..."] --> P["frozen profile QWEN-Q8-DYADIC-Q16-v0, profile_id 1ce6c47f..."]
    P --> R["row-order GEMM: FrozenQwen.gemm, row chunks outer, per-block scalar accumulation"]
    P --> C["column-stream GEMM: ColumnStreamQwen.gemm, column blocks outer, one vectorized exact int64 matmul per block"]
    R --> DR["24 layer digests + final logits + final hidden sha256"]
    C --> DC["24 layer digests + final logits + final hidden sha256"]
    DR --> EQ{"digests equal 24/24 and match preserved lineage?"}
    DC --> EQ
    EQ -->|"yes"| PASS["gate PASS, exit 0"]
    EQ -->|"no"| KILL["kill: order semantics leaked, re-freeze under new profile_id"]

Figure 1 — Handshake v0, probe 2: two independently derived GEMM implementations execute the same frozen profile on the same real weights; layer digests are equal 24/24, final logits and hidden hashes match, and both match the preserved 1ce6c47f… lineage (runs/integer_24layer_prompt.json) — gate PASS. A single digest mismatch kills C2's premise. MEASURED 2026-07-10.

Schedule gate (schedule_gate.py, pre-existing). The same invariance attacked from the scheduling side: one layer-0 GEMM computed under five adversarial schedules (canonical, reversed, tiled_shuffled, split_k, tree_walk) with digest comparison per schedule, plus an FP32 shadow computing the same quantity in float under the same five schedules as a negative control. The integer profile must produce one digest; the shadow is expected to splinter — and does (C3).

Probe 1 — SiLU clipping baseline (silu_probe.py). Hooks all 24 FFN gate-activation sites of the fixed prompt (145,920 values per layer; 3,502,080 total) and scores two LUTs against stdlib float SiLU (math.exp, stable sigmoid, x = q/2¹⁶ in float64): the frozen profile's 65537-entry Q11-domain ±16 table, and the committed NEL-L0 harness table from nel-dispute-ladder/harness/layer_ref.py (int8 domain ±8, Q4 output, activations rescaled Q16→Q4 by add-half shift). Purpose: no SiLU-clipping threshold existed anywhere in the program; this run creates the baseline the next profile revision must beat.

Probe 3 — divergence root-cause (divergence_probe.py). Re-runs the integer profile on prompt + the 6 agreed tokens and captures llama.cpp CPU logprobs live (same llama-server invocation as run_llama_compare.py: -t 4 -ngl 0 -fa 0, temperature 0, top_k 1, seed 42, dynamically chosen free port; fallback to the preserved runs/llama_compare.json only if live capture fails its prefix sanity check — this run used live, and the live logprobs were bit-identical to the preserved capture, consistent with cpu_repeat_bit_exact=TRUE). It dumps integer top-10 logits and llama top-10 logprobs at the divergent step, computes the pairwise gap in each frame, and measures an FP-noise yardstick: the max common-top20 logprob delta between llama.cpp CPU and Vulkan fa0 over steps 0–6. Classification rule fixed in advance: {quantized-logit tie within FP rounding distance | genuine profile drift | sampling detail}; "cause open, bounded to X" is an acceptable verdict if the gap is sub-rounding.

Results

Table 1 — independent-implementation determinism MEASURED 2026-07-10 (source: runs/second_impl.json):

Table 2 — adversarial schedule gate, layer-0 GEMM, 4-token prefix MEASURED 2026-07-10 (source: runs/schedule_gate.json):

integer_schedule_gate=TRUE; fp32_shadow_diverged=TRUE — 1 integer digest across 5/5 schedules versus 4 distinct FP32 bit patterns across the same 5 schedules.

Table 3 — SiLU LUT baseline, 3,502,080 gate activations, range [−31.87, +44.27] real units MEASURED 2026-07-10, baseline-creating (source: runs/silu_clip.json):

Worst layers (frozen LUT): layer 21 — act range [−31.8669, +44.2683], max err 28.2683, 30/41 clips; layer 3 — act max 31.0021, max err 15.0021, 4/41 clips. Off the clip tail the frozen LUT is essentially exact (mean 6.8e-05); negative-side clips are harmless (|silu(−16)| ≈ 1.8e-06). Verdict on the committed table: any NEL-L0-style profile for this model class needs a wider SiLU domain and a finer output grid.

Table 4 — token-7 divergence, step 6, pair 25963 (" reflects") vs 374 (" is") MEASURED 2026-07-10 (sources: runs/divergence_probe.json, runs/integer_generation_16.json):

Top of both distributions (candidates >3 logits clear of #3 in each frame): integer top-3 — 374 → 20.1898, 25963 → 20.1732, 90011 → 16.9193 (real units, Q16/2¹⁶); llama CPU top-3 logprobs — 25963 → −0.6720, 374 → −0.8856, 90011 → −4.0680. Sampling detail excluded: greedy settings and the chosen token equals argmax of returned logprobs (llama_greedy_honest=TRUE).

xychart-beta
    title "Token-7 pair 25963 vs 374: absolute logit gap by frame, against measured FP noise"
    x-axis ["llama CPU", "llama Vulkan fa0", "integer profile", "FP noise bound"]
    y-axis "absolute logit gap" 0 --> 0.25
    bar [0.213574, 0.075470, 0.016586, 0.237414]

Figure 2 — Token-7 divergence, step 6: absolute pairwise logit gaps on the pair 25963 (" reflects") vs 374 (" is"). Signed values: llama.cpp CPU +0.213574, llama.cpp Vulkan fa0 −0.075470, integer profile −0.016586 — llama's own two backends flip sign on the pair, and all three frames sit inside the measured cross-implementation FP noise bound 0.237414. MEASURED 2026-07-10.

Classification: quantized-logit tie within FP rounding distance. llama.cpp's own two backends flip sign on the pair (+0.214 CPU vs −0.075 Vulkan) on identical context; the CPU margin at the split (0.2136) is below the measured cross-implementation FP noise (0.2374) and is the smallest of all seven decisions; the integer profile lands inside the same noise band and sides with Vulkan 16/16. CPU→integer pair drift 0.230160 < FP noise 0.237414, so no component of the offset is attributable to profile drift at this step. Cause open only in the sense that the FP backends themselves define no ground truth here; bounded to ≤ 0.23 logits on this pair.

flowchart TD
    S["step 6 split: integer picks 374, llama.cpp CPU picks 25963"] --> B["llama's own backends flip sign on the pair: CPU +0.213574, Vulkan fa0 -0.075470"]
    B --> N["FP noise yardstick: max common-top20 logprob delta, CPU vs Vulkan, steps 0-6 = 0.237414"]
    N --> Q{"pair drift CPU frame to integer frame 0.230160 < 0.237414?"}
    Q -->|"yes"| T["classification: quantized-logit tie within FP rounding distance"]
    Q -->|"no"| D["genuine profile drift - declared as such, not absorbed as a tie"]
    T --> V["consistent: integer matches Vulkan 16/16; offset bounded to 0.23 logits on this pair"]

Figure 3 — The divergence-classification decision: the CPU→integer pair drift (0.230160) is below the measured cross-implementation FP noise (0.237414), so no component of the offset is attributable to profile drift — a quantized-logit tie. A future split at a margin exceeding the noise bound on its window would be declared genuine profile drift (falsifier 5). MEASURED 2026-07-10.

METRIC anchors (from nel-real-inference/README.md): silu_values_total=3502080, silu_frozen_max_abs_err=28.268280029, silu_frozen_mean_abs_err=0.000067981, silu_frozen_clip_events=41, silu_nel_l0_max_abs_err=36.330780029, silu_nel_l0_mean_abs_err=0.018280265, silu_nel_l0_clip_events=1166, second_impl_digests_equal=TRUE, integer_matches_vulkan_16_of_16=TRUE, integer_schedule_gate=TRUE, fp32_shadow_diverged=TRUE.

Falsifiers & kill thresholds

A kill is a deliverable. Standing tripwires:

1. Gate 1 / E-NEL-01 — the load-bearing open falsifier. Run the frozen profile's integer kernels on ≥2 GPU vendors (CUDA + ROCm/Vulkan) plus CPU and compare digests. Kill threshold: a single bit of digest divergence between conforming implementations on different silicon kills the vendor-invariance claim outright — no tolerance, no averaging. Until that run exists, this paper claims CPU-scale evidence only. (B1 gap table G4 + G5; the AMD leg has zero published evidence in any lane, from anyone.)
2. Second-implementation divergence. Any future conforming implementation producing a mismatched layer digest (against 1ce6c47f… lineage on the fixed prompt) proves order-of-evaluation semantics leaked into the profile spec — kill of C2's premise, profile must be re-frozen under a new profile_id.
3. One schedule-dependent bit. A single mismatched cell across adversarial schedules at any scale kills the order-invariance premise (C3) and with it the free-by-construction argument (C6).
4. SiLU clip tripwire. The frozen ±16 domain measurably clips real activations (41/3,502,080; worst err 28.27 at layer 21). If any future decode divergence or accuracy failure traces to a clip event, the SiLU domain is re-frozen (new profile_id). The committed NEL-L0 table is already past its kill line for this model class — 1,166 clips and 1.8e-02 mean error on real Qwen activations — and is recorded as unfit; that negative result stands.
5. Divergence-classification falsifier. The C5 classification dies if a future integer-vs-llama.cpp split occurs at a decision margin exceeding the measured FP cross-implementation noise on its window: that would be genuine profile drift and must be declared as such, not absorbed as a tie.
6. Accuracy kill (B1 G3, open). Accuracy collapse of the frozen profile at 0.5B scale beyond kill-criterion-8 tolerance kills the profile even if determinism holds. The 16-token probe is evidence of plausibility, not an accuracy validation.
7. Vendor integer-dot-product deviation. A GPU vendor whose integer dot product deviates from two's-complement exactness (no known instance; cheaply testable inside the Gate 1 harness) would force per-vendor conformance carve-outs and weaken the profile to a whitelist.

Reproduction

Handshake v0 probes (cwd nel-real-inference; Python 3.10 + numpy; each run is minutes — a real 0.5B on CPU; model at models/qwen2.5-0.5b-instruct-q8_0.gguf, sha256 ca59ca7f…):

# cwd: nel-real-inference
python silu_probe.py           # probe 1 -> runs/silu_clip.json
python second_impl_gate.py     # probe 2 -> runs/second_impl.json  (gate PASS, exit 0)
python divergence_probe.py     # probe 3 -> runs/divergence_probe.json (needs llama-server.exe, see below)

Pre-existing pipeline the README documents (same cwd): python integer_generate.py (greedy 16-token generation vs llama.cpp CPU → runs/integer_generation_16.json), python run_llama_compare.py (llama.cpp CPU/Vulkan determinism + logprob capture via llama-server.exe from llamacpp/bin, -t 4 -ngl 0 -fa 0, temperature 0, top_k 1, seed 42 → runs/llama_compare.json, runs/server_*.json), python schedule_gate.py (adversarial-schedule gate → runs/schedule_gate.json), python accuracy_probe.py (accuracy vs float). The divergence probe falls back to the preserved runs/llama_compare.json if live llama-server capture is unavailable; the llama_source field in its output records which path was used.

Expected anchors: second_impl.json:gate="PASS", digests_equal=true, elapsed_s={10.64, 13.87}; silu_clip.json:aggregate per Table 3; divergence_probe.json:classification="quantized-logit tie within FP rounding distance", gaps.llama_frame_logits=0.213574, fp_noise.max=0.237414; schedule_gate.json:integer_schedule_gate=true, fp32_shadow_diverged=true.

Related work

What is not new: integer-only transformer arithmetic, LUT nonlinearities, and same-platform deterministic serving all exist and are measured elsewhere. The contribution here is the composition target — one frozen, hashable integer profile whose bit-pattern is implementation- and schedule-independent on real weights — plus the negative-space honesty that the cross-vendor leg is untested by anyone, including us. External references below are those already collected in the B1 memo (noosphere/research/nel-b1-determinism-memo.md); dossier paths are on-disk.

• Thinking Machines, "Defeating Nondeterminism in LLM Inference" (He et al., 2025, DOI 10.64434/tml.20250910) — the diagnosis this paper builds on: no atomics in the forward pass; nondeterminism = batch-variant FP reduction order; batch-invariant kernels at 1.6–2.1× cost. The integer profile removes the constraint instead of paying for it.
• SGLang deterministic inference (LMSYS blog, 2025-09-22; avg 34.35% slowdown) and vLLM VLLM_BATCH_INVARIANT (NVIDIA SM80+ only) — production same-platform FP determinism; explicitly not cross-hardware.
• cuBLAS reproducibility docs (same toolkit + same arch + same SM count + single stream only) and PyTorch reproducibility notes (no cross-platform or CPU/GPU promise) — vendors actively disclaim what Gate 1 demands.
• I-BERT (arXiv:2101.01321), I-ViT (arXiv:2207.01405), I-LLM (arXiv:2405.17849) — integer nonlinearities and integer-only execution at BERT/ViT/LLaMA scale, historically faster than FP32 (2.4–4.0× on T4; 3.72–4.11× on 2080 Ti); none ships a bit-exactness or conformance test, and integer RoPE is unclaimed territory the frozen profile fills.
• Verde/RepOps (arXiv:2502.19405) and RepDL (github.com/microsoft/RepDL) — the FP alternative: pin the FP operation order. FP32-only, four NVIDIA GPUs, +58% (A100) to +218% (T4) on Llama-1B inference; the integer route makes the same guarantee free.
• opML (arXiv:2401.17555) — determinism via a pinned MIPS VM semantics; the precedent for "determinism by spec," orders of magnitude off production speed.
• T-MAC (arXiv:2407.00088), bitnet.cpp (arXiv:2410.16144), BitNet b1.58 2B4T (arXiv:2504.12285) — LUT/ternary integer cores wrapped in FP glue (FP32 absmax scales, FP norms/softmax); "lossless" is not a bit-exactness claim, and no cross-device bit-identity test is published.
• TFLite/LiteRT int8 spec + gemmlowp requant — the strongest existing consensus-numeric-profile precedent (FP-free dyadic requant); CNN-era op set, and hardware delegates are held to tolerances, not bit-identity. ONNX QLinearMatMul/QuantizeLinear — FP32 scales in the spec make it unusable as a consensus profile as-is.
• Groq TSP (ISCA 2020) — deterministic production inference hardware exists; single-vendor, no help for a heterogeneous committee.
• Pearl cuPOW — GPU FP matmul kernels without a determinism or verification story: research/08-pearl-matmul-pow.md, digest noosphere/research/02-pearl-cupow-kernel-digest.md.
• Octra HFHE — determinism via homomorphic-ciphertext semantics rather than an integer profile; different trust model: noosphere/research/01-octra-hfhe-consensus-digest.md.